The present invention relates to a translation lookaside buffer for translating a virtual address into a real address at a high speed and, particularly, to an address translation unit suitable for speeding up the translation process where multilevel address translation tables with extended virtual address are used.
Among hierarchically structured address translation tables for translating a virtual address into a real address, there have been used tables of two-level structure as described in the IBM Manual: System 370 Principle of Operation (GA22-7000-8), Section: Dynamic Address Translation.
However, when the virtual address is extended significantly from 31 bits to 64 bits, for example, the two-level hierarchical structure is not sufficient, but it is natural to arrange a multi-level hierarchical structure as high as five levels. The reason is that, if the execution with the address extension is left at two-levels a large number of entries is necessary for the translation table, and a large continuous memory area for the translation table is required. By the arrangement of a multi-level hierarchical structure, the size of the continuous memory area can be reduced.
A deficiency resulting from the multi-level structure is the impairment of process performance when the entry does not exist in the translation buffer which is provided for the speed-up of translation. A two-level structure causes a memory request to be initiated twice, while five-level structure requires a memory request to be initiated five times.